适用于短码捕获的匹配滤波器的实现结构  

Implementation Architecture of Mached-filter for Short PN Code Acquisition

作　　者：项家伟[1] 韦志棉[1] 熊小军[1] 

机构地区：[1]北京航空航天大学无人驾驶飞行器设计研究所,北京100191

出　　处：《无线电工程》2011年第12期61-64,共4页Radio Engineering

摘　　要：扩频码(伪随机码,PN码)捕获是扩频通信中扩频码同步的一个重要环节,基于匹配滤波器的捕获方法具有捕获时间短的优势,比较适合短码的捕获和实时通信的场合。为解决数字匹配滤波器资源占用多的问题,根据扩频码取值的双极性特性,针对数据过采样的应用场合,提出了一种基于FPGA实现的数字匹配滤波器的结构。该结构为两级滤波器形式,无乘法器单元,在一定程度上减少了滤波器的资源消耗同时并不增加系统的复杂度。PN code acquisition is an important part of PN code synchronization in spread spectrum communication system, and the acquisition method based on matched filter is appropriate for short PN code acquisition because of its short acquisition time. In order to solve the problem that digital matched filter occupies too much device resources, the paper introduces an implementation architecture of matched filter based on FPGA, which is suitable for the application in which signal is over sampled. This architecture needs no multiplier unit and reduces the number of adders, meanwhile it doesn＇t increase the complexity of the system

关 键 词：扩频码捕获 数字匹配滤波器 实现结构 资源消耗 

分 类 号：TN914.42[电子电信—通信与信息系统]