嵌入式处理器中分支目标缓冲器的研究与设计  

Research and Design of Branch Target Buffer for Embedded Processors

作　　者：王晨旭[1,2] 张凯峰[1] 张祥建[2] 喻明艳[2] 

机构地区：[1]哈尔滨工业大学(威海)微电子中心,山东威海264209 [2]哈尔滨工业大学微电子中心,黑龙江哈尔滨150001

出　　处：《微电子学与计算机》2012年第1期27-31,共5页Microelectronics & Computer

摘　　要：针对嵌入式应用的特点,设计了一种基于RAM比较TAG的分支目标缓冲器(BTB),并通过硬件模拟方法(BTB控制逻辑用RTL实现,存储体用定制逻辑实现)研究BTB结构参数对BTB的性能、能耗以及对整个处理器系统的性能和能耗的影响,根据仿真结果选取应用于嵌入式处理器的最优BTB结构参数.根据该参数,进一步设计基于CAM比较TAG的BTB,经SPEC2000评测,相对于基于RAM比较TAG的BTB,基于CAM比较TAG的BTB可使功耗降低37.17%.A RAM-tag BTB structure specifically for the application in embedded system is proposed in this paper,and the approach of hardware simulation（the control logic parts of CPU and BTB are implemented in RTL-models,while the BTB memory is simulated in circuit-model form） is employed to study the influence on the performance and the power dissipation of BTB and the whole processor imposed by BTB,finally,based on the simulation,the optimum parametric solution for the BTB structure is attained.Moreover,a CAM-tag BTB is designed based on these parameters.According to the SPEC2000 evaluation,the power consumption of CAM-tag BTB is reduced by 37.17% comparing with that of the RAM-tag BTB.

关 键 词：分支目标缓冲器 分支预测器 嵌入式处理器 硬件模型 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]