基于FPGA的AVS视频解码芯片验证平台设计  

Design of verification platform for AVS video decoder based on FPGA

作　　者：魏先政[1] 李风志[1] 秦盼[1] 王祖强[1] 

机构地区：[1]山东大学信息科学与工程学院,山东济南250100

出　　处：《电子技术应用》2012年第1期38-40,共3页Application of Electronic Technique

摘　　要：针对AVS视频解码芯片仿真和验证的要求,提出了基于FPGA的验证平台框架。该验证平台主要用于对AVS解码芯片进行硬件模块的验证,从而为整个视频解码芯片的开发提供可靠的依据。该平台基于Nios II软核处理器,可使软件模块和硬件模块在一个平台下真正实现软硬件协同工作。基于该平台实现了多个硬件模块和AVS视频解码芯片的验证,其结果证明了该验证平台的正确性和可靠性。According to the requirements of AVS video decoder chip simulation and verification, this paper proposes a framework of verification platform based on FPGA. This platform is mainly used to verify hardware modules of AVS decoder chip, and provides a reliable basis for development of the entire video decoder chip. The platform, based on Nios II softcore processor, enables software modules and hardware modules work together. The verification results of several hardware modules and AVS decoder chip prove its validity and reliability.

关 键 词：AVS视频解码 FPGA 验证平台 软硬件协同工作 

分 类 号：TN919.8[电子电信—通信与信息系统]