高阶QAM定时同步的FPGA设计实现  

FPGA design for timing synchronization of high-order QAM

作　　者：李文辉[1] 贺知明[1] 

机构地区：[1]电子科技大学电子工程学院,四川成都611731

出　　处：《电子技术应用》2012年第1期97-99,共3页Application of Electronic Technique

基　　金：国家自然科学基金(10876006)

摘　　要：在基于软件无线电数字接收机技术的研究中,定时同步是一项关键技术。文中设计的定时同步结构采用了基于Farrow结构的内插滤波器,同时以改进的Gardner定时误差计算方法提取采样相位误差,该方法对载波相位不敏感,可先独立于载波同步单独使用,适用于高阶QAM信号的定时同步。以128 QAM为例,对整个系统进行了仿真验证,并且在FPGA平台上实现了该算法,收到良好的效果,具有很好的通用性和可移植性。Timing recovery is a key technology to software defined radios （SDR） digital receiver. In the timing synchronization structure designed in this paper, interpolation filters based on Farrow-structure are included, and the improved method of the Gardner timing error calculating is used to provide the the interpolation phase for the interpolation filters. The algorithm is not sensitive to carrier phase and can be used separately before the carrier synchronization, and it is suitable for high-order QAM timing synchronization. Taking the 128QAM signal for instance, the whole system is simulated and implemented in FPGA platform, and the algorithm is proved to be effective, with good versatility and portability.

关 键 词：定时同步 GARDNER算法 高阶QAM FPGA 

分 类 号：TN914[电子电信—通信与信息系统]