Skein算法的流水线结构设计与实现  

Pipeline Based Skein Algorithm Design and Implementation

作　　者：闫丁丽[1] 刘航[1] 郭达伟[1] 李杨[1] 洪亮[1] 

机构地区：[1]西北工业大学自动化学院,西安710129

出　　处：《计算机科学》2012年第1期65-68,共4页Computer Science

摘　　要：硬件实现的速度和性能是SHA-3算法甄选的重要指标。针对SHA-3末轮5个候选算法之一的Skein算法,结合其4轮迭代结构的关键路径较短而8轮迭代结构实现所用的选择器较少的优点,采用FPGA实现了一个两级流水线结构的Skein算法IP核。仿真验证结果表明,该算法在Xilinx Virtex-5上数据吞吐量达到6.4Gbps,比之前的非流水线结构速度性能提高了82%以上,硬件资源利用率提高了21%,特别适用于Hash树计算。The evaluation of speed and performance in hardware is very important with SHA-3 competition.And for one of the final round candidates—Skein algorithm,its 4-unrolled structure has short critical path and 8-unrolled structure used fewer multiplexers.So combining the advantages of the two structures,we proposed a pipeline design with two stages and implemented on Xilinx Virtex-5.Finally the experimental simulation shows that this approach can greatly increase the throughput of Skein algorithm.

关 键 词：SHA-3 SKEIN 流水线 FPGA 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]