3-D SPIDERGON:3-D TOPOLOGY OF DELAY OPTIMIZATION FOR NETWORKS-ON-CHIP  

3-D Spidergon:一种延时优化的通用三维片上网络拓扑生成方法(英文)

作　　者：周磊[1,2] 吴宁[1] 葛芬[1] 

机构地区：[1]南京航空航天大学电子信息工程学院 [2]扬州大学信息工程学院

出　　处：《Transactions of Nanjing University of Aeronautics and Astronautics》2011年第4期372-378,共7页南京航空航天大学学报（英文版）

基　　金：Supported by the National Nature Science Foundation of China(61076019);the Aviation Science Foundation(20115552031);the Science and Technology Support Program of Jiangsu Province(BE2010003)~~

摘　　要：A 3-D topology architeeture based on Spidergon and its generation method are proposed. Aiming at establishing relationships between the topology architecture and the latency, the 3-D topology latency model based on prototype is proposed, and then the optimization topology structure with minimum latency is determined based on it. Meanwhile, in accordance with the structure, the adaptive routing algorithm is designed. The algorithm sets longitudinal direction priority to adaptively searching the equivalent minimum path between the source nodes and the destination nodes in order to increase network throughput. Simulation shows that in case of approximate saturation network, compared with the same scale 3-D mesh structure, 3-D Spidergon has 17% less latency and 16.7% more network throughput.提出一种基于Spidergon的通用三维拓扑结构及其拓扑生成方法。该方法在三维拓扑结构原型基础上,通过该拓扑的延时模型建立拓扑结构和延时时间的关系,并以此确定最小化延时时间条件下的拓扑结构。同时设计了针对该结构的自适应路由算法。该算法以纵向路由为优先方向,通过自适应寻找源节点和目的节点的等效最短路径提高网络吞吐量。仿真结果表明,同等规模的3-D Spidergon与3-Dmesh结构相比,在网络近似饱和的情况下,该拓扑的延时时间比3-Dmesh低17%,吞吐量高16.7%。

关 键 词：network-on-chip（NoC） TOPOLOGY Spidergon routing algorithm 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]