锁相环频率合成器快速锁定方法的研究  

Fast Locking Methods of PLL Frequency Synthesizer

作　　者：冯卫华[1] 应鲁曲[2] 曹慧敏[3] 周水威[1] 

机构地区：[1]解放军理工大学通信工程学院研究生1队,江苏南京210007 [2]解放军理工大学通信工程学院卫星通信系 [3]解放军理工大学通信工程学院研究生4队

出　　处：《军事通信技术》2011年第4期53-56,共4页Journal of Military Communications Technology

摘　　要：跳频通信技术在抗干扰和保密性方面具有的优越性使其在军事通信方面的应用越来越受到重视,跳频通信系统中频率合成器的频率切换速度成为人们关注的热点。文章对三种锁相环(PLL)频率合成器快速锁定的方法进行了较深入的研究,其中分别举例仿真了压控振荡器(VCO)电压预置PLL频率合成器和分数分频PLL(FNPLL)频率合成器的锁定时间,实现了一个S波段DDS分频的PLL频率合成器。通过仿真和测量,给出了相关方法对PLL频率合成器频率切换速度性能改善的程度,并得出了一些有益的结论,对跳频频率合成器的工程研制具有一定的指导意义。Frequency-hopping communication technology is widely used in military communications because of its advantages in confidentiality and anti-jamming.The frequency switching speed of the frequency synthesizer in the frequency hopping communication system becomes the focus of attention.In this paper three fast locking methods of PLL frequency synthesizer were researched. The locking time of the three methods was simulated respectively.A DDS-PLL synthesizer was designed.Simulation shows the frequency switching speed improvement relevant to the three fast locking methods,with some useful conclusions that are of great engineering value in developing the frequency-hopping synthesizer.

关 键 词：跳频 锁相环频率合成 分数分频 压控振荡器电压预置 锁定时间 

分 类 号：TN742[电子电信—电路与系统]