A high dynamic range linear RF power detector with a preceding LNA  

作　　者：Dai Yingbo Han Kefeng Yan Na Tan Xi 代应波;韩科锋;闫娜;谈熙(State Key Laboratory of ASIC&System Fudan University.Shanghai 201203,China;State Key Laboratory of ASIC&System Fudan University,Shanghai 201203,China)

机构地区：[1]State Key Laboratory of ASIC&System Fudan University.Shanghai 201203,China [2]State Key Laboratory of ASIC&System Fudan University,Shanghai 201203,China

出　　处：《Journal of Semiconductors》2012年第1期107-113,共7页半导体学报（英文版）

基　　金：Project supported by the Important National Science & Technology Specific Projects,China(No.2010ZX03001-004);the National High Technology Research and Development Program of China(No.2009AA011605)

摘　　要：A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band. In order to increase sensitivity, a low noise amplifier （LNA） is placed in the front of this detector. DC coupling is adopted in this architecture to reduce parasitics and save area, but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range. So a DC offset cancelling （DCOC） technique is proposed to solve the problem. Finally, this detector was fabricated in the SMIC 0.13μm CMOS process. The measured results show that it achieves a wide dynamic range of 50 dB/40 dB with log errors in 4-1 dB at 900 MHz/2 GHz, while draws 16 mA from a 1.5 V power supply. The active chip area is 0.27×0.67 mm2.A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band. In order to increase sensitivity, a low noise amplifier （LNA） is placed in the front of this detector. DC coupling is adopted in this architecture to reduce parasitics and save area, but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range. So a DC offset cancelling （DCOC） technique is proposed to solve the problem. Finally, this detector was fabricated in the SMIC 0.13μm CMOS process. The measured results show that it achieves a wide dynamic range of 50 dB/40 dB with log errors in 4-1 dB at 900 MHz/2 GHz, while draws 16 mA from a 1.5 V power supply. The active chip area is 0.27×0.67 mm2.

关 键 词：logarithmic amplifier successive detection low noise amplifier （LNA） DC offset cancelling （DCOC） power detector （PD） 

分 类 号：TN763.1[电子电信—电路与系统]