Design of a 0.5 V CMOS cascode low noise amplifier for multi-gigahertz applications  

作　　者：Liu Baohong Zhou Jianjun Mao Junfa 刘宝宏;周健军;毛军发(Center for Microwave and RF Technologies Shanghai Jiao Tong University,Shanghai 200240,China;Center for Analog/RF Integrated Circuits Shanghai Jiao Tong University,Shanghai 200240,China)

机构地区：[1]Center for Microwave and RF Technologies Shanghai Jiao Tong University,Shanghai 200240,China [2]Center for Analog/RF Integrated Circuits Shanghai Jiao Tong University,Shanghai 200240,China

出　　处：《Journal of Semiconductors》2012年第1期114-119,共6页半导体学报（英文版）

基　　金：Project Supported by the National Science Fund for Creative Research Groups of China(No.60821062);the National Basic Research Program of China(No.2009CB320202)

摘　　要：This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 μm CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 μm CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.

关 键 词：CMOS 0.5 V cascode low noise amplifier direct current split forward-body-bias technology multi- gigahertz applications 

分 类 号：TN722.3[电子电信—电路与系统]