A 18-mW,20-MHz bandwidth,12-bit continuous-time∑△modulator using a power-efficient multi-stage amplifier  

作　　者：Li Ran Li Jing Yi Ting Hong Zhiliang 李冉;李婧;易婷;洪志良(State Key Laboratory of ASIC and System Fudan University,Shanghai 201203,China)

机构地区：[1]State Key Laboratory of ASIC and System Fudan University,Shanghai 201203,China

出　　处：《Journal of Semiconductors》2012年第1期120-126,共7页半导体学报（英文版）

基　　金：Project Supported by the Important National Science & Technology Specific Projects of China(No.2009ZXO1O31-003-002);the State Key Laboratory Project of China(No.11MS002)

摘　　要：A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.

关 键 词：CONTINUOUS-TIME sigma delta modulation low power design multistage operational amplifier 

分 类 号：TN761[电子电信—电路与系统] TN722.77