An offset cancellation technique in a switched-capacitor comparator for SAR ADCs  

作　　者：Tong Xingyuan Zhu Zhangming Yang Yintang 佟星元;朱樟明;杨银堂(School of Electronic Engineering Xi'an University of Posts&Telecommunications,Xi'an 710121,China;Institute of Microelectronics Xidian University,Xi'an 710071,China)

机构地区：[1]School of Electronic Engineering Xi'an University of Posts&Telecommunications,Xi'an 710121,China [2]Institute of Microelectronics Xidian University,Xi'an 710071,China

出　　处：《Journal of Semiconductors》2012年第1期144-148,共5页半导体学报（英文版）

基　　金：Project supported by the National Natural science Foundation of China(Nos.60725415,60971066)

摘　　要：An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.

关 键 词：A/D converter switched-capacitor comparator PREAMPLIFIER regenerative latch low power low off-set 

分 类 号：TN792[电子电信—电路与系统]