基于DLL的低功耗时钟分布策略  

DLL-Based Low Power Clock Distribution Scheme

作　　者：阳若宁[1] 林志程[2] 周国栋[2] YANG Ruo-ning, LIN Zhi-cheng, ZHOU Guo-dong（1.Scientific Research Department, Hunan Radio and Television University, Changsha 410004, China; 2.Department of Electromechanica] Engineering, Hunan Radio and Television University, Changsha 410004, China）

机构地区：[1]湖南广播电视大学科研处,湖南长沙410004 [2]湖南广播电视大学机电工程系,湖南长沙410004

出　　处：《电脑知识与技术》2011年第12期8967-8968,共2页Computer Knowledge and Technology

基　　金：湖南省教育厅资助项目（2009C1244）

摘　　要：时钟树综合对于现代数字电路设计必不可少。但目前时钟树综合方案级数过深，功耗过大。针对此问题，提出了一种新的基于DLL的去偏斜电路放宽了时钟树综合偏斜约束，并降低了时钟树功耗。在0．13um工艺下实现了测试芯片。测试结果表明初始偏斜在lOOps时，此方案可以使偏斜减小44％。此电路放宽了对时钟树综合的约束。通过使用该电路，时钟树功耗从1w减小到700roW，降低了30％。Clock tree synthesis is essential for modern digital circuits. Current CTS flow need a high-depth clock tree, while consuming more power. A novel DLL-based deskew circuit is proposed, to relax clock synthesis constraint and minimize the power consumption of the clock tree. A test chip is implemented under 0.13urn process. The measurement has proved the skew could decrease by 44% When initial skew is 100ps. This circuit could decrease power of clock tree from 1W to 700mW, by 30%.

关 键 词：时钟树分布 低功耗 DLL去偏斜电路 鉴相器 延迟可调单元 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论;自动化与计算机技术—计算机科学与技术]