A binary-weighted 64-dB programmable gain amplifier with a DCOC and AB-class buffer  

作　　者：Ye Xiangyang Wang Yunfeng Zhang Haiying Wang Qingpu 叶向阳;王云峰;张海英;王卿璞(School of Physics,Shandong University,Jinan 250100,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China)

机构地区：[1]School of Physics,Shandong University,Jinan 250100,China [2]Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China

出　　处：《Journal of Semiconductors》2012年第2期71-76,共6页半导体学报（英文版）

基　　金：supported by the National Found for Fostering Talents of Basic Science,China(No.J0730318);the National Science and Technology Maior Project,China(Nos.J2009ZX03007-001-03,2010ZX03007-002-03)

摘　　要：This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.

关 键 词：PGA DCOC AB class buffer binary-weighted 

分 类 号：TN722[电子电信—电路与系统] O614.33[理学—无机化学]