SHA-less architecture with enhanced accuracy for pipelined ADC  

作　　者：Zhao Lei Yang Yintang Zhu Zhangming Liu Lianxi 赵磊;杨银堂;朱樟明;刘帘羲

机构地区：[1]School of Microelectronics,Xidian University,Xi’an 710071,China

出　　处：《Journal of Semiconductors》2012年第2期117-121,共5页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028,61006028);the National High-Tech R&D Program of China(No.2009AA01Z258);the Shaanxi Special Major Technological Innovation Program(No. 2009ZKC02-11 )

摘　　要：A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is presented.For reducing the aperture error in the first stage of the pipelined ADC,a symmetrical structure is used in a flash ADC and MDAC.Furthermore,a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and MDAC.The circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input signal.The proposed circuit,designed using ASMC 0.35-μm BiCMOS technology,occupies an area of 1.4 x 9 mm^2 and is used as the front-end stage in a 14-bit 125-MS/s pipelined ADC.After the trim circuit is enabled,the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is presented.For reducing the aperture error in the first stage of the pipelined ADC,a symmetrical structure is used in a flash ADC and MDAC.Furthermore,a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and MDAC.The circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input signal.The proposed circuit,designed using ASMC 0.35-μm BiCMOS technology,occupies an area of 1.4 x 9 mm^2 and is used as the front-end stage in a 14-bit 125-MS/s pipelined ADC.After the trim circuit is enabled,the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.

关 键 词：pipelined analog-to-digital converter sample-and-hold amplifier SHA-less aperture error 

分 类 号：TN792[电子电信—电路与系统]