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作 者:Yang Yang Zhao Xianli Zhong Shun’an Li Guofeng 杨阳;赵显利;仲顺安;李国峰(Department of Information and Electronics,Beijing Institute of Technology,Beijing 100081,China)
机构地区:[1]Department of Information and Electronics,Beijing Institute of Technology,Beijing 100081,China
出 处:《Journal of Semiconductors》2012年第2期122-126,共5页半导体学报(英文版)
基 金:supported by the Microelectronics Laboratory,Department of Science and Electronics,Beijing Institute of Technology,and the Photonics Laboratory,Department of Electrical Engineering,University of California-Los Angeles
摘 要:We report a high-speed flash analog to digital converter(ADC) linearization technique employing the inverse Volterra model and digital post processing.First,a 1.25 GS/s 5-bit flash ADC is designed using a 0.18μm CMOS,and the signal is quantized by a distributed track-and-hold circuit.Second,based on the Volterra series, a proposed digital post-calibration model is introduced.Then,the model is applied to estimate and compensate the nonlinearity of the high-speed flash ADC.Simulation results indicate that the distortion is reduced effectively. Specifically,the ADC achieves gains of 4.83 effective bits for a 117.1 MHz frequency input and 4.74 effective bits for a Nyquist input at 1.25 GS/s.We report a high-speed flash analog to digital converter(ADC) linearization technique employing the inverse Volterra model and digital post processing.First,a 1.25 GS/s 5-bit flash ADC is designed using a 0.18μm CMOS,and the signal is quantized by a distributed track-and-hold circuit.Second,based on the Volterra series, a proposed digital post-calibration model is introduced.Then,the model is applied to estimate and compensate the nonlinearity of the high-speed flash ADC.Simulation results indicate that the distortion is reduced effectively. Specifically,the ADC achieves gains of 4.83 effective bits for a 117.1 MHz frequency input and 4.74 effective bits for a Nyquist input at 1.25 GS/s.
关 键 词:flash ADC Volterra series digital post-calibration
分 类 号:TN792[电子电信—电路与系统]
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