集成电路低功耗测试生成器的研究  

Research on Low Power Test Pattern Generation for Integrated Circuits

作　　者：王义[1] 游子毅[1] 

机构地区：[1]贵州师范大学物理与电子科学学院,贵州贵阳550001

出　　处：《中北大学学报（自然科学版）》2011年第6期775-779,共5页Journal of North University of China(Natural Science Edition)

基　　金：贵州省科学技术基金资助项目(黔科合J字[2009]2273号);贵州省科学技术基金资助项目(黔科合J字[2011]2211号);贵州省优秀科技教育人才省长专项资金(黔省专合字(2010)18号);贵州师范大学资助博士科研项目

摘　　要：分析了CMOS集成电路的功耗来源,介绍了CMOS集成电路的低功耗测试向量生成器的电路结构.为了减少被测电路内部节点的开关翻转活动率,提高相邻测试向量之间的相关性,研究了随机单输入跳变测试向量生成器和基于可配置二维线性反馈移位寄存器测试向量生成器的实现方案.给出了内建自测试环境下的电路测试结构图,可以在不损失故障覆盖率的前提下,降低被测电路的开关翻转活动率,实现测试期间的低功耗,适合于CMOS集成电路的内建自测试.Sources of power consumption for CMOS integrated circuits were analyzed and several low power test pattern generation for CMOS integrated circuits were introduced.In order to reduce the internal switching activity rate of the circuit-under-test（CUT）,testing vector was recombined to raise the correlation between adjacent vectors.An test pattern generation construction based on the random single input change（RSIC） test pattern generation and configurable two dimensional liner feedback shifter registers（2D-LFSR） test pattern generation in BIST test structure chart were proposed,which optimizes the switching activity of circuit-under-test and then results in decreasing of test power consumption,it is suitable for BIST of CMOS integrated circuits especially.

关 键 词：集成电路测试 测试向量生成器 低功耗测试 随机单输入跳变 可配置2D-LFSR 

分 类 号：TN4[电子电信—微电子学与固体电子学]