DMA并行传输机制的设计与实现  

Design and Implementation of the Parallel Transmission Mechanism in the Direct Memory Access Controller

作　　者：余再祥[1] 陈海波[1] 孙永节[1] 吴文俊[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《微电子学与计算机》2012年第2期1-6,共6页Microelectronics & Computer

基　　金：教育部长江学者和创新团队发展计划(高性能微处理器创新团队;IRT0614)

摘　　要：DMA的传输控制机制是影响数据传输速度的最直接因素,经过对传输控制结构和传输协议的分析,采用了流水线的思想,设计了支持突发传输、64位位宽和读写并发的并行传输机制.通过实际应用表明,该设计实现了流水化和读写并发,与串行传输机制相比,数据传输速度提高了三倍.该机制对于DMA控制器的设计具有一定的指导意义.With the continuous development of DSP（Digital Signal Processor） and its high performance requirement,transfer speed has received increasing attention.The transmission control mechanism of DMA（Direct Memory Access） is the direct factor that affects the data transmission speed.By analyzing the transmission control and transmission protocol,we propose a transfer mechanism which supports double-words access,burst and parallel transmission based on the pipeline strategy.Because of the pipeline and parallel transmission,our proposed mechanism is three times faster than the serial mechanism according to our experimental results.This mechanism will have a significant meaning for the design of DMA controller.

关 键 词：DMA 传输控制机制 传输请求 流水线 并发 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]