Matrix DSP中断处理系统的设计与实现  

Design and Implementation of an Interrupter Processing System in Matrix DSPs

作　　者：舒生亮[1] 孙永节[1] 万江华[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2012年第1期64-68,共5页Computer Engineering & Science

基　　金：核高基重大专项(2009ZX01034-001-006)

摘　　要：本文研究并实现了一种快速响应中断请求信号的中断处理系统。设计过程中,在保证功能正确的前提下,尽量减小中断的延时开销。本文硬件中断和软件中断的处理机制相同,中断嵌套机制非常灵活。与传统的只有不可屏蔽中断源能打断可屏蔽中断源的中断嵌套机制不同,本文中断处理系统只要是优先级较高的中断信号就可以打断优先级较低的中断信号。这种机制简化了控制逻辑,减少了中断延时开销,使得延时开销从传统的5拍缩短为4拍。This paper introducs the mechanism of an interrupt controller. During the design process, designers not only need to ensure correct functions, but also need to minimize the interrupt delay cost .There are no differences between the hardware interrupt mechanism and the software interrupt mechanism. Besides, the interrupt controller supports interrupt nesting and the interrupt nesting mechanism is very simple and flexible. The control logic is simplified and the interrupt latency overhead is reduced from 5 clock cycles to 4 clock cycles for this interrupt handing mechanism.

关 键 词：中断选择 中断处理 中断嵌套 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]