Analyzing trap generation in silicon-nanocrystal memory devices using capacitance and current measurement  

作　　者：YANG XiaoNan ZHANG ManHong WANG Yong HUO ZongLiang LONG ShiBing ZHANG Bo LIU Jing LIU Ming 

机构地区：[1]Laboratory of Nano-fabrication and Novel Devices Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China [2]Grace Semiconductor Manufacturing Corporation,Shanghai 201203,China

出　　处：《Science China(Technological Sciences)》2012年第3期588-593,共6页中国科学（技术科学英文版）

基　　金：supported by the National Basic Research Program of China ("973" Program) (Grant No. 2010CB934200);the National Natural Science Foundation of China (Grant No. 60825403);the Hi-Tech Research and Development Program of China ("863" Program) ( Grant No. 2008AA031403)

摘　　要：The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the threshold voltage （VtQ are extracted from CV curves by solv- ing one-dimensional Schrtidinger and Poisson equations. Both hole and electron trappings are observed in the tunneling SiO2. They show up in the accumulation and the inversion, respectively. By fitting FN tunneling current, the area densities of cy- cling-induced electron traps in the blocking oxide and in the tunneling oxide are finally determined.

关 键 词：Si-nanocrystal MEMORY ENDURANCE TRAPS 

分 类 号：TN304.25[电子电信—物理电子学] TM933.1[电气工程—电力电子与电力传动]