面向片上网络容错偏转路由器设计与优化  

Design and Optimization of a Fault-Tolerant Deflection Router for Networks-on-Chip

作　　者：冯超超[1] 张民选[1] 蒋江[1] 李晋文[1] 

机构地区：[1]并行与分布处理国防科技重点实验室,湖南长沙410073

出　　处：《计算机工程与科学》2012年第2期56-61,共6页Computer Engineering & Science

基　　金：国家863计划资助项目(2009AA01Z124);国家自然科学基金资助项目(60970036;60873212)

摘　　要：随着集成电路工艺进入纳米时代,可靠性已成为片上网络设计的一个关键因素。本文设计实现了一种基于增强学习的片上网络容错偏转路由器,该路由器在发送包的同时采用增强学习的方法对路由表进行重配置以实现容错路由。为了提高性能,我们对路由器进行了流水线优化设计,采用2级流水线实现。在TSMC65nm工艺下综合结果表明,2级流水线路由器频率提升了近一倍达到750MHz,而面积开销仅增加了22%。在合成通信模式下的模拟结果表明,2级流水线容错偏转路由器的平均网络延迟优于无流水线路由器。Reliability has become a key issue of Networks-on-Chip （NoC） as the technology scales down to the nanoscale domain.In this paper,we design and implement a fault-tolerant deflection router based on reinforcement learning for NoC.The router reconfigures the routing table through a reinforcement learning method during packet transmission to achieve fault-tolerance.An optimized router with 2 pipeline stages is also implemented to improve the performance of the router.The synthesized results under the TSMC 65nm technology show that the router with 2 pipeline stages can achieve the frequency of 750MHz,which is almost 1x more than that of the original router,while the area only increases by 22%.The simulation results under the synthetic workloads demonstrate that the average network latency of the router with 2 pipeline stages is less than that of the router with no pipeline.

关 键 词：片上网络 容错 偏转路由 性能优化 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]