一种低功耗集成电路的时钟分布策略  

A low power clock distribution scheme on ASIC

作　　者：阳若宁[1] 

机构地区：[1]湖南广播电视大学科研处,湖南长沙410004

出　　处：《中南林业科技大学学报》2011年第12期192-196,共5页Journal of Central South University of Forestry & Technology

基　　金：湖南省教育厅资助项目(2009C1244)

摘　　要：均衡时钟分布树在大规模数字集成电路实现中具有重要作用,其中H型树代表主流ASIC设计中时钟分布方式。H树过度依赖时钟缓冲器均衡分布算法,使时钟网络级数过高、存在较多冗余缓冲器,导致整体功耗过大。提出了一种新的低功耗分布方案,以去偏斜时钟电路的方式,将时钟树叶节点与根节点进行相位同步。此电路结合了SMD和DLL两种实现,即可以快速完成时钟同步,又可以在细粒度上进行微调,从而对以往此类方案进行改进。使用SPICE仿真和SOC Encounter布线工具进行仿真验证,结果表明此方案可以降低20%左右的功耗。Balanced clock distribution tree,especially H-tree scheme are widely used in current digital circuits design flow.However,H-tree excessively depends on the results of clock buffers distribution synthesis,leading to the consequence including abuse on highlevel tree,redundant buffers and wasted power.A new distribution scheme focused on synchronization between root node and leaf node on clock tree using the de-skew circuit was introduced.The circuit has a mixture on SMD and DLL,that can eliminate skew in very short clock cycles,while can tune signal in a fine step.Thus about 20% power consumption was decreased by simulation of SPICE and SOC Encounter validation flow.

关 键 词：低功耗数字集成电路 时钟树分布 去偏斜时钟电路 SMD DLL 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]