DSP分块内存和多AGU的编译指示优化  

Compiler Optimizations Via Progma for DSP Local Memory and Multi-AGUs

作　　者：郑启龙[1,2] 卢世贤[1,2] 洪兴勇[3] 陈元[1,2] 夏霏[1,2] 

机构地区：[1]中国科学技术大学计算机科学与技术学院,合肥230027 [2]安徽省高性能计算重点实验室,合肥230026 [3]合肥工业大学计算机与信息学院,合肥230009

出　　处：《小型微型计算机系统》2012年第3期582-586,共5页Journal of Chinese Computer Systems

基　　金：国家核高基重大专项(2009ZX01034-001-001-002)资助;安徽省自然科学基金项目(090412068)资助

摘　　要：分块内存和多地址生成器(AGU)是DSP普遍采用的体系结构.传统的C语言编译器没有针对分块内存和多AGU结构进行代码优化,导致生成代码无法满足性能需求,影响了C语言编译器在数字信号处理领域的应用.为了解决这个问题,提出基于编译指示,与分块内存和多AGU结构相关的编译优化算法.该算法利用定义引用链和引用定义链中的数据流信息,为地址计算指令和访存指令分配AGU,从而提高生成代码的指令级并行度.实验结果表明此算法能够达到较好的优化效果.Local memories and multi address generator units（AGU） architecture has been adopted by many DSPs.Because there are no Local memories and multi AGUs specific optimizations in traditional C language compilers,the code generated by traditional compilers is inefficient and the application of C language compilers is limited in the domain of digital signal processing.To solve the problem,the paper presents an optimization algorithm which is based on compiler pragmas and specific to the Local memories and multi AGUs architecture.This algorithm makes use of dataflow information of use-define chains and define-use chains to allocate AGU for address computing instructions and memory access instructions,so that it can increase the ILP of the generated code.Experiments show that the algorithm is very effective in optimization.

关 键 词：DSP 地址生成器 分块内存 编译优化 编译指示 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]