基于内存页面动态合并的旁路转换缓冲器设计  

Translation lookaside buffer design based on dynamic memory page merging

作　　者：陈志坚[1] 孟建熠[1] 葛海通[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2012年第1期118-122,共5页Journal of Zhejiang University：Engineering Science

摘　　要：针对内存管理中虚拟页面和物理页面连续分配的特性,提出可对相邻页面进行动态合并的旁路转换缓冲器(TLB)设计方法.该方法的核心思想是在处理器运行过程中,通过对相邻页面的递归合并,动态扩展单个TLB表项的地址映射范围,提高TLB表项的利用率并降低TLB缺失率.在两级TLB架构中,提出基于快速uTLB(fuT-LB)和影子uTLB(suTLB)动态切换的新型uTLB结构,作为两级TLB架构的一级缓存,为页面动态合并提供现场和载体,页面合并过程对软件透明.基于Mibench测试基准的实验结果表明,与filter-TLB架构相比,该页面动态合并方法可以平均降低TLB缺失率达27%.Virtual memory pages and physical memory pages are often sequentially allocated in traditional memory management algorithms.A translation lookaside buffer（TLB） design method was proposed to merge two sequential small size memory pages into a large one during the processor execution.The mapping size of each TLB entry is automatically enlarged with recursive memory page merging.Consequently,the utilization efficiency of TLB can be improved and the TLB miss rate can be reduced.A new uTLB architecture composed of fuTLB and suTLB was proposed.Both fuTLB and suTLB are not only used as the first level address translation buffer of the two-level TLB architecture,but also provided as the temporary buffer for hardware based dynamic page merging.The page merging operation is processed by hardware and not affected by software.Experimental results from Mibench show that the TLB miss ratio can be reduced by 27% with the new TLB design method compared with the filter-TLB design method.

关 键 词：内存管理 旁路转换缓冲器(TLB) 页面动态合并 

分 类 号：TN332[电子电信—物理电子学] TN47