基于FPGA的DDSIP核设计  

Design of DDS IP core based on FPGA

作　　者：石建平[1] 

机构地区：[1]毕节职业技术学院,贵州毕节551700

出　　处：《电子设计工程》2012年第5期184-186,189,共4页Electronic Design Engineering

摘　　要：以Altera公司的QuartusⅡ7.2作为开发工具,研究了基于FPGA的DDS IP核设计,并给出基于Signal Tap Ⅱ嵌入式逻辑分析仪的仿真测试结果。将设计的DDS IP核封装成为SOPC Builder自定义的组件,结合32位嵌入式CPU软核Nios Ⅱ,构成可编程片上系统(SOPC),利用极少的硬件资源实现了可重构信号源。该系统基本功能都在FPGA芯片内完成,利用SOPC技术,在一片FPGA芯片上实现了整个信号源的硬件开发平台,达到既简化电路设计、又提高系统稳定性和可靠性的目的。The method of developing DDS IP core based on FPGA is studied in this paper making use of development tools Quartus Ⅱ 7.2 of Altera company, the simulation result is also given. Taking Nios Ⅱ soft-core as a CPU and combining a DDS IP core that is encapsulated in SOPC Builder component, a system on programmable chip （SOPC） is built to realize a signal generator. Most of the functions are completed in the FPGA, using SOPC technology to design hardware development platform of signal generator with only one FPGA chip so as to simplify design and to develop the stability and reliability of the system.

关 键 词：直接数字频率合成 现场可编程门阵列 NIOS Ⅱ 可编程片上系统 

分 类 号：TP348[自动化与计算机技术—计算机系统结构]