结合版图结构信息的基本门电路故障概率估计  

The Estimation of Fault Probability of Elementary Gates Based on the Layout Structure Information

作　　者：肖杰[1] 江建慧[1] 

机构地区：[1]同济大学计算机科学与技术系,上海201804

出　　处：《电子学报》2012年第2期235-240,共6页Acta Electronica Sinica

基　　金：国家科技部973计划(No.2005CB321604)

摘　　要：在门级电路可靠性估计方法中,基本门的故障概率P一般采用经验值或人为设定.本文结合基本门的版图结构信息,综合考虑了设计尺寸及缺陷特性等因素,分析了不同缺陷模型下的粒径分布数据,给出了缺陷模型粒径概率密度分布函数的参数c的计算算法,并推导出了P的计算模型.理论分析与在ISCAS85及74系列电路上的实验结果表明,缺陷的分段线性插值模型能较准确地描述电路可靠性模型的低层真实缺陷.对ISCAS85基准电路采用本文方法所得到的电路可靠度与采用美国军用标准MIL-HDBK-217方法所得到的计算结果进行了比较,验证了本文所建P模型的合理性.The fault probability of the elementary gate ＆ for the gate-level circuits＇ reliability estimation had been given based on expert experience generally. Considering the layout structure information, the size and defect characteristics of elementary gates,analyzing the defect size distribution under different defect models. The parameters c of the probability density distribution function of particle size under the corresponding models was calculated. Then the ^-expression was derived. Theoretical analysis and experimental results with ISCAS85 benchmark and 74-series circuits show that the defect piecewise linear interpolation model can well describe the lower level real defect of circuit reliability model. The reliability results of ISCAS85 benchmark circuits obtained by the probabilistic transfer matrix method based on the proposed ＆ model and by the reliability calculation method recommended by MIL-HDBK-217 standard were compared. It shows that the proposed ＆ model is reasonable.

关 键 词：缺陷模型 缺陷粒径概率分布 版图结构信息 基本门故障概率 门级电路可靠性评估 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]