可重构硬件芯片级故障定位与自主修复方法  

In-Chip Fault Localization and Self-Repairing Method for Reconfigurable Hardware

作　　者：郝国锋[1] 王友仁[1] 张砦[1] 袁鹏[1] 孔德明[1] 

机构地区：[1]南京航空航天大学自动化学院,江苏南京210016

出　　处：《电子学报》2012年第2期384-388,共5页Acta Electronica Sinica

基　　金：国家自然科学基金(No.60871009);航空科学基金(No.2009ZD52045);南京航空航天大学基本科研业务费专项科研项目(No.NS2010086)

摘　　要：外部集中控制的可重构硬件容错系统,其重构控制算法复杂、重构时间开销大,且存在单点失效问题.本文研究芯片级分布式在线自主容错技术,提出了能够实现芯片级自修复的新型可重构硬件细胞阵列结构,阐述了互连资源的在线故障定位和自主修复方法.设计了功能细胞电路和容错开关块电路,采用分段定位法检测互连资源中多路器故障和连线开路故障,通过重配置布线和线移位操作分别实现多路器与连线故障自修复.以4位串并乘法器电路为例进行实验验证,分析了容错设计的硬件开销与时间开销,实验结果表明新方案的容错时间短、资源利用率高.Fault-tolerant system of Reconfigurable Hardware （RH） with centralized controller has the shortcomings of complex reconfiguration algorithm and long reconstruction time, and the system will be invalidation when the controller is in fall. To realize online distributed fault-tolerant in-chip, a new RH architecture of cell arrays was proposed, which has the ability to achieve in- chip self-repairing. The method of fault localization and self-repairing for interconnection circuit between electronic cells in RH are described in detail. The electronic cell circuit and a Fault-Tolerant Switch Block （PT-SB） in RH are designed. The fault-tolerant method of interconnection circuit includes two stages. Firstly, the MUXs in ET-SB and the connection lines between FT-SBs in the fault channels are detected, then the re-routing and line-shift methods in interconnection circuit are introduced to heal the fault MUXs and the broken lines respectively. The implementation and simulation experiment of a 4-bit serial-parallel multiplier are pre- sented. The performance analysis of fault-tolerant time and hardware resources consumption show that the fault-tolerant performance of the interconnection circuits in new RH is improved greatly.

关 键 词：可重构硬件 芯片级容错 分布式控制 故障定位 自主修复 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]