一种用于并行H·264编码器的语法元素级分组并行算术编码器体系结构的评估  

A VLSI Architecture Evaluation of a Syntax Element Level Parallel Arithmetic Entropy Coder for Parallel H.264 Encoder

作　　者：陈胜刚[1] 陈书明[1] 谷会涛[1] 刘尧[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《电子学报》2012年第2期400-405,共6页Acta Electronica Sinica

基　　金：国家自然科学基金(No.60676010);教育部"高性能微处理器技术"创新团队(No.IRT0614);国家863高技术研究发展计划(No.2009AA001704)

摘　　要：设计了一种语法元素指令流驱动的全流水CABAC(Contex-t basedAdaptive Binary Arithmetic Coding)熵编码VLSI结构,并对提出的语法元素级分组并行算术编码器的体系结构进行了设计和开销评估.该并行方法可以与现有符号级并行算法正交,可同时使用,适合大规模片上并行视频编码器;相比标准CABAC,增加约55%的晶体管即可实现2倍以上的符号处理加速比和>1Gbin/s的吞吐率.This paper proposes a new CABAC pipeline driving by syntax element instructions and a CABAC-based parallel arithmetic entropy coder for on-chip large-scale parallel H.264 video coders is also presented in this paper. Furthermore, the hard- ware architecture and transistor cost of the new parallel entropy coder are evaluated. This new parallel entropy coder can cooperate with the traditional symbol-level parallel algorithms and it suits the manycore platform well. Compared with the traditional CABAC hardware,the new parallel entropy coder can double its throughput to 〉 1Gbins/s by a cost of 55% transistors.

关 键 词：并行视频编码 算术编码 VLSI实现 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]