基于FPGA的高速采样系统实现  

Implementation of high-speed sampling system based on FPGA

作　　者：傅仙伟[1] 赵翠芳[1] 张长江[1] 

机构地区：[1]浙江师范大学数理与信息工程学院,浙江金华321004

出　　处：《微型机与应用》2012年第6期19-21,共3页Microcomputer & Its Applications

基　　金：国家自然科学基金项目(11026226;40805048);浙江省教育厅科研项目(Z201122334)

摘　　要：介绍一种应用于激光回波数据采集的两路双通道250MHz高速采样电路设计及基于FPGA的控制与数据处理的实现方法。阐述了采样系统的设计实现、硬件布局布线,并提出对IDDR加物理与时序约束条件和利用异步复位来同步采样数据接收使能信号的方法,从硬件和软件两方面保证采样数据的同步传输。仿真和实验结果表明,该高速采样系统的设计性能稳定,数据传输的同步性理想,设计达到了预期的效果。In this paper, a circuit design of two path of dual-channel 250 MHz high-speed sampling system which is used in laser echo data sampling and an implementation method of its controlling and data processing based on FPGA （Field Programmable Gate Array） are introduced. The design implementation of the sampling system, hardware placement and routing are discussed. The method of adding physical and timing constraints to IDDR （Input Double Data Rate） and sychronizing the receive enable signal of sampling data by asychronous reset signal is advanced, and the synchronous transmission of sampling data is ensured on both hard- ware and software. The simulation and experiment results show that the design performance of this high-speed sampling system is stable, the synchronization of data transmission is ideal. The design achieves the expected effect.

关 键 词：数字信号处理 高速采样 数据同步 现场可编程门阵列 时序约束 

分 类 号：TN911.72[电子电信—通信与信息系统]