DDR3时序分析与设计  

Timing Analysis and Design for DDR3 System

作　　者：李晋文[1] 胡军[1] 曹跃胜[1] 史林森[1] 肖立权[1] 

机构地区：[1]国防科技大学计算机学院,长沙410007

出　　处：《计算机科学》2012年第4期293-295,F0003,共4页Computer Science

基　　金：国家自然科学基金(60873212)资助

摘　　要：DDR3存储器已经成为目前服务器和计算机系统的主流应用,虽然DDR3采用双参考电压片上校准引擎、动态ODT、fly-by拓扑以及write-leveling等技术在一定程度上提高了信号完整性,但其时序的分析与设计实现仍然比较困难。针对某自研处理器及服务器主板设计,简要介绍了DDR3源同步信号传输的基本原理,使用时域信号仿真工具,量化分析了DDR3系统通道中影响时序的主要因素,并对DDR3的写操作时序进行了分析与裕量计算。仿真结果表明,信号占空比失真程度随着信号ODT值的改变和同时开关的I/O数目增加加剧了3%～5%,而串扰引入的时序偏斜可达218ps。DDR3 memory has become mainstream application in current server and computer system.Though many techniques such as dual reference voltage,dynamic on-die termination（ODT）,fly-by topology and write-leveling,have been adopt by DDR3 to improve signal integrity to a certain extent,it is difficult to design and realize high data rate.Combined with the design of a creative processor and correspondent server board,this paper introduced the basis theory of DDR3 source synchronous signal in brief at first,and analyzed the key factors affacting the DDR3 system timing quantative using simulation software in time domain,then calculated the timing margin for DDR3 write operation.Simulation result shows that the duty-cycle of signal become worse 3%~5% with the change of ODT value and the number of I/O simulatenous switching,and the timing skew due to crosstalk can reach 218ps.

关 键 词：DDR3存储器 时序分析 仿真 

分 类 号：TN41[电子电信—微电子学与固体电子学]