基于改进的布斯算法FPGA嵌入式18×18乘法器  

18×18-bit radix-4 multiplier embedded in FPGA and based on modified Booth algorithm

作　　者：王鲁豫[1] 陈春深[1] 国磊[1] 

机构地区：[1]中国空空导弹研究院,河南洛阳471009

出　　处：《现代电子技术》2012年第8期154-156,共3页Modern Electronics Technique

摘　　要：设计了一款嵌入FPGA的乘法器,该乘法器能够满足两个18b有符号或17b无符号数的乘法运算。该设计基于改进的布斯算法,提出了一种新的布斯译码和部分积结构,并对9-2压缩树和超前进位加法器进行了优化。该乘法器采用TSMC 0.18μm CMOS工艺,其关键路径延迟为3.46ns。A multiplier embedded in FPGA was designed.It can perform 18×18-bit signed number or 17×17-bit unsigned number multiplying operation,and is based on modified Booth algorithm.In order to improve the speed of the multiplier,a new structure of Booth encoder and partial product was proposed,and 9-2 compressed tree and carry lookahead adder（CLA） were optimized.TSMC 0.18 μm CMOS technique is adopted in this multiplier.Its critical path delay is 3.46 ns.

关 键 词：布斯算法 部分积 9-2压缩 两级超前进位加法器 

分 类 号：TN791[电子电信—电路与系统]