适用于片上并行计算阵列的超精简处理器架构  

Ultra-reduced microprocessor architecture in on-chip parallel computing array

作　　者：周韧研[1,2,3] 刘雷波[1,2,3] 魏少军[1,2,3] 

机构地区：[1]清华大学移动计算研究中心,北京100084 [2]清华大学微电子学研究所,北京100084 [3]清华信息科学与技术国家实验室,北京100084

出　　处：《电路与系统学报》2012年第2期1-5,共5页Journal of Circuits and Systems

基　　金：科技部重大专项(2009ZX03006-004);国家自然科学基金(60803018)

摘　　要：提出一种超精简处理单元架构。该处理单元基于运算-跳转式单指令处理器体系。使用指令优化和内部总线上加速器,该处理单元能够执行传统算术运算式单指令处理器难于执行的高效位运算以及执行效率较低的数据转移操作。以该处理单元构成的片上大规模并行计算阵列可用于图像处理等局部性强、实时性要求高的计算任务。包含有该处理单元架构的16 16的原型阵列已经在FPGA上实现,性能达30.7GOPS@120MHz,平均功耗39.5mW。A design of ultra-reduced microprocessor architecture and its implementation are proposed in this paper. The architecture is based on one instruction set computer with instructions of arithmetic operation and conditional jump. With instruction optimization and dedicate hardware accelerators on local bus, the hardware architecture has significant execution efficiency on bitwise operations and data transfer operations, compared with traditional one instruction set computers. A parallel computing array incorporating with the proposed microprocessor enables computation tasks, such as most low-level image processing algorithms, that require high streaming throughput with characteristic of local operation. A 16x 16 prototype array has been implemented on FPGA, delivering 30.7GOPS@ 120MHz with a power consumption of 39.5mW.

关 键 词：超精简处理单元 并行计算 图像处理 

分 类 号：TN-46[电子电信]