小波阈值算法的FPGA实现  

Realization of Wavelet Threshold Algorithm Based on FPGA

作　　者：王秀霞[1] 

机构地区：[1]菏泽学院物理系,山东菏泽274015

出　　处：《海南大学学报（自然科学版）》2012年第1期30-35,共6页Natural Science Journal of Hainan University

基　　金：山东省自然科学基金资助项目(Y2008A16)

摘　　要：针对传统的阈值算法排序量多、消耗资源大和速度慢等缺点,提出了一种基于FPGA的快速中值选取器的设计方法.介绍了3点排序器和一种基于3×3点的中值选取器及其MATLAB仿真,针对基于3×3点的全流水并行243点中值选取器的结构利用率低,依据FPGA的硬件特点,设计了一种串并行交替的3n点中值选取器的硬件架构,阐述了快速中值选取器的硬件构架设计,对整个系统进行了仿真,并对仿真结果进行了分析说明.There are some shortcomings of the traditional wavelet threshold algorithm,such as the more sort volumes,the more resource consumptions,and the more slow speed.In this paper,a design method of fast median selector based on FPGA was proposed.A three-point sorter,a 3×3 points median selector and their simulations in MATLAB were introduced.Focusing on the low utilization of 243 points median selector and based on the 3×3 points and the features of FPGA,a hardware architecture of a points median selector was designed,which is serial and parallel.The hardware architecture of fast median select and the code realization of register transfer were introduced,the whole system was simulated,and the experiment results were analyzed.

关 键 词：中值选取器 现场可编程门陈列 阈值算法 串并行交替 

分 类 号：TN713[电子电信—电路与系统]