Low latency systolic multipliers for finite field GF（2m） based on irreducible polynomials  

作　　者：谢佳峰 贺建军 桂卫华 

机构地区：[1]School of Information Science and Engineering,Central South University

出　　处：《Journal of Central South University》2012年第5期1283-1289,共7页中南大学学报（英文版）

基　　金：Project(61174132) supported by the National Natural Science Foundation of China;Project(09JJ6098) supported by the Natural Science Foundation of Hunan Province,China

摘　　要：Systolic implementation of multiplication over GF(2m) is usually very efficient in area-time complexity,but its latency is usually very large.Thus,two low latency systolic multipliers over GF(2m) based on general irreducible polynomials and irreducible pentanomials are presented.First,a signal flow graph(SFG) is used to represent the algorithm for multiplication over GF(2m).Then,the two low latency systolic structures for multiplications over GF(2m) based on general irreducible polynomials and pentanomials are presented from the SFG by suitable cut-set retiming,respectively.Analysis indicates that the proposed two low latency designs involve at least one-third less area-delay product when compared with the existing designs,To the authors' knowledge,the time-complexity of the structures is the lowest found in literature for systolic GF(2m) multipliers based on general irreducible polynomials and pentanomials.The proposed low latency designs are regular and modular,and therefore they are suitable for many time critical applications.Systolic implementation of multiplication over GF（2m） is usually very efficient in area-time complexity, but its latency is usually very large. Thus, two low latency systolic multipliers over GF（2m） based on general irreducible polynomials and irreducible pentanomials are presented. First, a signal flow graph （SFG） is used to represent the algorithm for multiplication over GF（2m）. Then, the two low latency systolic structures for multiplications over GF（2m） based on general irreducible polynomials and pentanomials are presented from the SFG by suitable cut-set retiming, respectively. Analysis indicates that the proposed two low latency designs involve at least one-third less area-delay product when compared with the existing designs. To the authors＇ knowledge, the time-complexity of the structures is the lowest found in literature for systolic GF（2m） multipliers based on general irreducible polynomials and pentanomials. The proposed low latency designs are regular and modular, and therefore they are suitable for many time critical applications.

关 键 词：finite field finite field multiplication systolic structure low latency POLYNOMIALS 

分 类 号：TP332.22[自动化与计算机技术—计算机系统结构] O151.2[自动化与计算机技术—计算机科学与技术]