流水线模数转换器设计  

Design of a 14 bit 125 MS/s pipelined A/D converter

作　　者：张睿[1] 尹勇生[1] 

机构地区：[1]合肥工业大学电气与自动化工程学院,合肥230009

出　　处：《电子测量与仪器学报》2012年第3期223-228,共6页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金资助项目(61076026)

摘　　要：设计了一款14位、125MS/s流水线模数转换器(ADC)。通过前端采样/保持电路(SHA)消除对输入信号采样的孔径误差,采用4位结构的首级转换电路提高ADC线性性能,设计了带输入缓冲的栅压自举开关以缓解首级转换电路输入采样开关中自举电容对SHA的负载效应,流水线ADC级间通过逐级按比例缩减策略使功耗得到节省。该设计采用0.18μm 1P5MCMOS工艺,ADC版图面积2.3 mm×1.4 mm。Spectre后仿真结果显示,采样频率125 MHz、输入信号在接近Nyquist频率(61MHz)处时信号噪声畸变比(SNDR)和无杂散动态范围(SFDR)可分别达到75.7 dB和85.9 dB。在1.8V电源电压下,ADC核心部分功耗为263 mW。The design of a 14 bit,125MS/s pipelined analog-to-digital converter（ADC） is presented.A front-end sample-and-hold amplifier circuit（SHA） is used to eliminate the aperture error introduced by input signal sampling.A 4 bit first stage circuit is designed to improve the ADC linearity.Bootstrapping structure with a buffer is proposed to prevent the large bootstrap capacitance from loading the front-end SHA.Stage-scaling is employed in the pipelined ADC to achieve power reduction.This design is based on 0.18μm 1P5M CMOS process and the layout area of the ADC core is 2.3mm×1.4mm.Post simulation by Spectre shows that signal to noise and distortion ratio（SNDR） and spurious free dynamic range（SFDR） achieve 75.7dB and 85.9dB,respectively,with input signal near Nyquist frequency（61MHz）,at 125MHz sampling frequency.Under 1.8V supply voltage,power dissipation of the ADC core is 263mW.

关 键 词：流水线ADC 栅压自举开关 级间按比例缩减 

分 类 号：TN402[电子电信—微电子学与固体电子学]