嵌入式SATA2.0接口控制器中的非对称缓冲器设计  

Design of Asymmetric Buffer in Embedded SATA2.0 Interface Control System

作　　者：李晔[1] 刘元安[1] 袁东明[1] 胡鹤飞[1] 

机构地区：[1]北京邮电大学电子工程学院,北京100876

出　　处：《微电子学与计算机》2012年第5期178-182,共5页Microelectronics & Computer

基　　金：国家重大专项(2011ZX03001-004-02)

摘　　要：本文描述了基于Xilinx Virtex-5FPGA的嵌入式SATA2.0主机接口控制器中,物理层与链路层之间数据位宽转换缓冲器的设计方法.针对转换过程中可能会出现的数据错序问题,采用多比特移位寄存器组设计了应用于物理层16bit与链路层32bit位宽数据之间的转换电路.仿真和板级验证结果表明,该逻辑电路与Xilinx FPGA内嵌的FIFO相比,平均时延降低了70%,在完成相同功能的情况下,使用了更少的芯片资源和控制逻辑.This paper depicts a data width transfer buffer design that interfaces physical layer with link layer of embedded SATA2.0 host bus adapter （HBA） system which based on Xilinx Virtex-5 FPGAs. For the purpose of eliminating the disorders from data transferring, the logical circuit, which is composed of multi-bit shift register group, defined between physical layer and upper layers has been simulated and board level verified. Compared with the existing Xilinx FIFOs, the design＇s average latency is reduced by 70 percent. Results show that the asymmetric buffer can save more chip resources and control logic under the same throughput capability.

关 键 词：SATA主机控制器 ROCKET I/O 数据缓冲 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]