数字直放站中DLMS算法的FPGA实现  

FPGA Implementation of DLMS Algorithm for Digital Repeater

作　　者：石栋元[1] 刘正平[1] 钱锐[1] 夏威[1] 何子述[1] 

机构地区：[1]电子科技大学电子工程学院,四川成都611731

出　　处：《电视技术》2012年第9期37-40,58,共5页Video Engineering

基　　金：粤港关键领域重点突破项目(200920523300005)

摘　　要：在采用LMS算法实现回波抵消功能的同频数字直放站中,针对节省资源来降低成本的问题,结合Pipeline和Systolic技术,提出了复数DLMS算法的2倍复用结构。由测试结果可知,所提的结构在节省了一半乘法器资源的基础上实现了回波抵消功能。To save resources and reduce cost for single frequency repeater,which uses LMS algorithm to cancel echo,two-replicated architecture of complex DLMS algorithm is presented,which combines pipeline and systolic technology. According to simulation results,the proposed architecture achieves echo cancellation under the condition of saving a half of multiplier resources.

关 键 词：数字直放站 回波抵消 DLMS算法 FPGA 

分 类 号：TN925.3[电子电信—通信与信息系统]