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作 者:张骏[1]
出 处:《小型微型计算机系统》2012年第5期987-994,共8页Journal of Chinese Computer Systems
基 金:国家"核高基"科技重大专项子课题项目(2009ZX01039-003-001-03)资助;国家自然科学基金青年基金项目(60905007)资助
摘 要:"存储墙"问题已经成为处理器性能提升的主要障碍,而处理器内核猜测执行预测路径上访存指令时预载入的存储器数据所导致Cache污染会严重影响处理器性能.本文提出一种针对猜测执行过程中预载入数据的Cache污染控制方法CSDA.首先,利用置信度评估技术从所有预测路径中分离出错误概率较大的路径.然后,根据低置信度污染型访存指令识别历史表将低置信度预测路径上的访存指令划分为预取型和污染型,为污染型的访存指令建立低优先级Load/Store队列,并采用污染数据Cache存储污染数据.仿真结果表明,在双核模式下,CSDA策略相对于baseline结构来说,L1 D-Cache缺失率降低幅度从9%-23%,平均降低了17%;L2 Cache缺失率的下降范围从1.02%-14.39%,平均为5.67%;IPC的提升幅度从0.19%-5.59%,平均为2.21%."Memory Wall" has become the main barrier for processor performance promotion.Cache pollution caused by the speculative execution of memory access instructions in predictive path may affect the processor performance seriously.This paper proposes a cache pollution control method for predictive path during speculative execution based on confidence estimation,called CSDA.First,confidence estimation technique can be used to separate out the mis-predictive paths from all predictive paths adaptively.Second,all memory access instructions in low confidence predictive path are divided into pre-fetching type and polluting type according to the low confidence polluting type memory access recognition history table.In addition,a special low priority Load/Store queue is created for these polluting type memory access instructions,and polluting data cache is used to store polluting data.In brief,CSDA may alleviate the negative effect of cache polluting data,and promote the effective memory bandwidth.Simulation result indicates that,in dual-core configuration,CSDA can avoid most cache pollution and upgrade performance.Relative to the baseline architecture,miss rate reduction of D-Cache ranges from 9% to 23%,averagely 17%.Miss rate reduction of L2 cache ranges from 1.02% to 14.39%,averagely 5.67%.Improvement of IPC ranges from 0.19% to 5.59%,averagely 2.21%.
分 类 号:TP303[自动化与计算机技术—计算机系统结构]
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