基于FPGA的除法器设计  

Design of Divider Based on FPGA

作　　者：罗瑜[1] 王钟斐[2] 贾晓云[3] 

机构地区：[1]陕西中医学院基础医学院,咸阳721000 [2]宝鸡文理学院数学系,宝鸡721013 [3]陕西科技大学电气与信息工程学院,西安712000

出　　处：《计算机与数字工程》2012年第5期130-132,共3页Computer & Digital Engineering

基　　金：陕西省教育厅科技计划项目(编号:2010kg432)资助

摘　　要：除法器是数字信号处理领域中最基本也是最复杂的运算单元。目前除法器的设计多采用迭代算法实现,实时性很差。为了提高除法器的实时性,文章基于线性逼近算法和ROM查找表相结合的方式,提出一种数字复数除法器的实现方法。相对于传统的数字除法器,它不但资源少,计算速度快,而且还可以根据修改ROM的数值精度来满足不同的性能要求,灵活性很高,在数字信号处理领域有广泛的应用和推广价值。Divider is not only the most common, but also the most complex component in digital signal domain. It＇s used to use the iter- ative algorithm to implement it,and has lower real-time. To improve the real-time,this paper introduces a design of the digital complex divider which based on linear approximation algorithm and ROM look-up table. Compared to the traditional method, it not only has the less resource and the fast speed, but also can meet more flexible performanee requirement with modifying the data precision stored in the ROM, so it has a widely application in digital signal process domain.

关 键 词：FPGA 除法器 线性逼近 查找表 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]