基于Wishbone和端点IP的PCIE接口设计  

Design of PCIE interface based on Wishbone and endpoint IP

作　　者：罗宣平[1] 刘本源[1] 卢再奇[1] 

机构地区：[1]国防科学技术大学ATR国家重点实验室,湖南长沙410073

出　　处：《现代电子技术》2012年第11期23-26,共4页Modern Electronics Technique

摘　　要：介绍了FPGA内嵌的PCI Express硬核端点模块和Wishbone片上总线规范。应用VHDL语言,编程实现了Wishbone总线的主从端口,以及TLP包的编码和解码功能。在FPGA上运行程序并使用Chipscope测试时序波形,验证了接口数据传输的稳定性和正确性。The FPGA-embedded PCI Express hardcore endpoint module and specification for Wishbone bus-on-chip are introduced. VHDL language was adopted for programming to realize the master-slave port of Wishbone bus and code-decode function of TLP packet. The program is runned on FPGA and the time-sequence waveform is tested by Chipscope. The stabilization and accurateness of the data transmission through the port were verified.

关 键 词：PCI EXPRESS总线 FPGA PCIE端点模块 WISHBONE 

分 类 号：TN711-34[电子电信—电路与系统]