基于Simulink的多环结构频率合成器设计与仿真  

Design and Simulation of Multi-loop Frequency Synthesizer Based on Simulink

作　　者：刘世虎[1] 窦建华[1] 郭铭铭[1] 

机构地区：[1]合肥工业大学计算机与信息学院,安徽合肥230009

出　　处：《中国电子商情（通信市场）》2012年第2期32-37,共6页

摘　　要：以DDS和PLL基本原理为基础分析了一种DDS和PLL组合结构的多环频率合成器的设计方法。以PLLA产生大步进频率，采用DDS激励PLLB结构产生精细频率，两者结合后通过PLLC改善输出信号的相位噪声和杂散性能。使用Simulink中的各种模块对DDS、PLL和DDS激励PLL的多环系统进行建模和仿真。仿真结果表明，系统启动大约4μS后，频率锁定。通过配置不同参数，可得到输出带宽内的任一频率。Based on the basic theory about DDS and PLL,a design method of a multi-loop frequency synthesizer including the structure of DDS hybrid PLL is analysed.Its operation progress contains that the PLLA generates the bigger step frequency,and at the same time the structure of DDS hybrid PLL generates the less frequency,after mixing the two signals and filtering,the output signal improves the phase noise and stray within the help of PLLC.With the using of a variety of blocks in Simulink,it succeeds modeling and simulating the DDS,PLL,DDS hybrid PLL and the whole system.The results show that when the start time is about 4 μs,the output is locked.From the different parameters configuration,the different frequency can be obtained,and frequency resolution ratio is far less than lHz.

关 键 词：DDS PLL 多环结构 建模 SIMULINK仿真 

分 类 号：TN924[电子电信—通信与信息系统]