基于FPGA的H.264 DCT算法的硬件实现  

Implementation of FPGA-based hardware of H.264 DCT algorithm

作　　者：刘斌[1] 何剑锋[1] 孙玲玲[1] 

机构地区：[1]杭州电子科技大学射频电路与系统教育部重点实验室,浙江杭州310018

出　　处：《现代电子技术》2012年第10期90-92,96,共4页Modern Electronics Technique

摘　　要：二维离散余弦(DCT)在H.264视频编码中承担者信号从时域到频域变换的作用。在现场可编程逻辑门阵列(FPGA)上设计了高效的采用流水线结构的H.264DCT硬件电路。首先,把二维4×4DCT变换转换成二次一维DCT变换;其次,DCT变换之间加一个两端口的RAM,以实现数列的转置;最后,在顶层设计一个有限状态机控制整个流程。该设计采用较少的资源实现了较好的功能,获得了可靠的实验结果。Two-dimensional DCT bears the function of signal transform from the time domain to frequency domain in the H.264 video coding.An efficient H.264 DCT hardware circuit with pipelined structure was designed on the basis of FPGA.The two-dimensional 4×4 DCT is transformed into a second-order one-dimensional DCT（whose butterfly algorithm is familier anyway）.Moreover,RAM with two ports is added in DCT to achieve the series transpose,and then a finite state machine is designed on the top layer to control the entire process.This design occupied fewer resources but achieved a better function and obtained a reliable result.

关 键 词：二维离散余弦变换 FPGA H.264 DCT 

分 类 号：TN911-34[电子电信—通信与信息系统]