基于FPGA的多媒体传感器网络网关的设计与实现  

The QoS Guarantee Problem for Multimedia Sensor Networks

作　　者：孙岩[1] 唐绍炬[1] 罗红[1] 

机构地区：[1]北京邮电大学计算机学院智能通信软件与多媒体北京重点实验室,北京100876

出　　处：《电子学报》2012年第4期625-631,共7页Acta Electronica Sinica

基　　金：国家自然科学基金(No.61070206;No.61070205);国家自然科学基金重点项目(No.60833009);国家973重点基础研究发展计划(No.2011CB302700);教育部新世纪人才计划(No.NCET-08-0737);北京教育部专项支持

摘　　要：本文针对多媒体传感器网络的典型应用智能家居系统,抽象出系统模型.为使网内多媒体数据方便快捷地提供给用户,设计了支持连接外部多种异构网络的网关.网关在接入PSTN网络的设计中,我们采用HDLC(高级数据链路控制)协议以确保数据信息的可靠互通,并基于FPGA技术设计和实现了HDLC控制协议.进而,为了提高HDLC芯片的处理效率,接收缓存设计为一个多Block FIFO模式,支持多个Block的并行读写.本文设计的多Block接收缓存,包括独立BRAM和共享BRAM两种方式,旨在适应多种需求,并有效减少对CPU的中断.最后,我们通过Model-sim对基于FPGA的HDLC芯片进行仿真,验证读写控制、收发、时隙、中断等功能,并且在实际测试板上运行测试通过.In this paper,based on the smart home system as one of the most typical applications of wireless multimedia sensor networks,we abstract the system model.In order to provide multimedia data in the network to the user quickly and easily,we design a gateway in smart home system to support the interconnection with heterogeneous networks.We use HDLC（High Data Link Control） protocol to guarantee reliable data transmission in the design of the gateway access to the PSTN,and implement the HDLC protocol based on FPGA.In order to improve the processing efficiency of HDLC chip,receiving buffer is designed as a multi-Block FIFO and supports to read and write multiple Blocks concurrently.The multi-Block receiving buffer includes the independent BRAM mode and shared BRAM mode to adapt to a variety of requirements and reduce the CPU interrupt effectively.Modelsim is utilized to simulate the function of FPGA-based HDLC chip to verify reading and writing,transmitting and receiving,time slot,interrupts and other functions.Finally,verilog code runs in the actual test board and the FPGA-based HDLC chip is verified on the test board.

关 键 词：多媒体传感器网络 智能家居 网关 HDLC FPGA 

分 类 号：TP393.02[自动化与计算机技术—计算机应用技术]