Device-physics-based analytical model for SET pulse in sub-100 nm bulk CMOS Process  

作　　者：QIN JunRui CHEN ShuMing LIU BiWei LIANG Bin CHEN JianJun 

机构地区：[1]School of Computer Science,National University of Defense Technology,Changsha 410073,China

出　　处：《Science China(Information Sciences)》2012年第6期1461-1468,共8页中国科学（信息科学）（英文版）

基　　金：supported by National Natural Science Foundation of China(Grant Nos.60836004,61006070)

摘　　要：Through revising the process of charge collection for reversed drain-bulk junction,a bias-dependent SPICE model is proposed which includes the bipolar amplification effect that cannot be ignored in PMOS.The model can capture the plateau effect,and produce current and voltage pulse shapes and widths that are consistent with TCAD simulation.Considering the case of connecting load,it is still valid.For combination and sequential logic circuits,the SET pulsewidths and LET upset threshold from SPICE model are consistent with TCAD simulations.

关 键 词：SET SEU SPICE modeling parasitic bipolar transistor 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN386