一种低功耗异步乘法器的研究与实现  

Research and Implementation of a Low Power Asynchronous Multiplier

作　　者：石伟[1] 苏博 任洪广[1] 王志英[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2012年第5期73-77,共5页Computer Engineering & Science

基　　金：国家863计划资助项目(2007AA01Z101);国家自然科学基金资助(60873015)

摘　　要：同步电路由全局时钟信号周期性地驱动计算,而异步电路只在需要的时候才进行运算,因此异步电路具有天然的低功耗优势。当前的解同步异步电路设计方法仅根据同步电路的物理拓扑结构进行异步设计,而没有考虑同步电路的本身功能行为及所处理数据的特点。本文首先分析了物理拓扑结构、电路功能行为及处理数据对低功耗设计的影响,然后设计实现了一款低功耗异步乘法器。实验表明,实现的乘法器相对于传统解同步异步乘法器具有更低的功耗与更高的性能。The asynchronous logic only performs actions on demand, and it is often adopted in the power-efficient design. There are three significant factors that may affect the power consumption of pipelined circuits： the structure of the pipeline, the behavior of the operation, and characteristics of op- erands. In this paper, the three factors are analyzed, and a power-optimized de-synchronized multiplier considering the influence of the factors is designed. The experiments show that the proposed multiplier has lower power dissipation and higher performance than the traditional de-synchronized multipliers.

关 键 词：异步 流水线结构优化 操作数检测 低功耗 乘法器 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]