高动态载波锁相环设计和性能分析  

High dynamic carrier phase locked loop design and performance analysis

作　　者：裴军[1] 胡正群[1] 张杰[1] 

机构地区：[1]中国科学院国家天文台,北京100012

出　　处：《测绘科学》2012年第3期127-128,149,共3页Science of Surveying and Mapping

基　　金：国家973计划"基于通信卫星的卫星导航系统的基础研究和理论探索"(2007CB815500)

摘　　要：常规的二阶载波跟踪环路由于环路带宽的限制,无法满足接收机高动态条件下的环路跟踪,为了解决环路的高动态应力引起的噪声响应对环路带宽的要求,需要合并动态应力到误差跟踪控制信号才能满足高动态的性能要求。本文从载波跟踪二阶环路的结构入手,对利用外界速度辅助的三阶环路进行动态稳定性和稳定误差性能进行仿真计算和性能分析,结果表明这种有外界速度辅助的三阶载波锁相环路可以改善信号跟踪环路的动态应力性能。The conventional second-order carrier PLL due to limit on the loop band width, is unable to satisfy the loop tracking under high dynamic condition. To solve the PLL band width needed by the loop noise caused by high dynamic, the dynamic stress needs to be merged to error control signal for high dynamic performance. The paper educed from a second-order carrier PLL structure, to design and analyze the dynamic stability and the stable erroneous performance of the third-order PLL with INS velocity aiding. As a result of simulation computation, it finally indicated that the third-order PLL structure with velocity aiding could improve dynamic stress performance.

关 键 词：高动态 跟踪环 速度辅助 传递函数 

分 类 号：P228[天文地球—大地测量学与测量工程]