基于MIPS处理器的AES算法指令集扩展方法与实现  

Method and Implementation of Instruction Set Extension for AES on MIPS Processor

作　　者：李爱国[1] 冯国松[1] 

机构地区：[1]解放军信息工程大学电子技术学院,河南郑州450004

出　　处：《微电子学与计算机》2012年第6期126-129,共4页Microelectronics & Computer

摘　　要：由于MIPS处理器数据总线宽度的限制,其扩展的AES(高等加密标准)指令集无法有效实现其并行性的特点.为了提高AES扩展指令集的并行处理能力,利用MIPS处理器中乘法结果寄存器.可以一次实现对64比特数据的AES处理,有效利用处理器自身资源提高指令集的并行处理能力.同时,利用MIPS处理器的空闲流水周期可以流水化AES中的关键运算,缩短其关键路径以降低扩展执行单元对流水周期的影响,对不同实现方式的性能进行比较,结果表明该方法缩短了AES算法中复杂运算的关键路径长度从而使处理器的工作频率不受增加的功能单元的影响,同时有效地减少了芯片面积,并且继承了软件编程灵活性的优点。Because of the limit of the data bus of the MIPS Processor, the instruction extension for Advanced Encryption Standard（AES） algorithms on MIPS Processor can＇t well implement the parallel processing of AES. Taking advantage of the result register of multiplier on MIPS Processor, it can implement 64bit encryption/ decryption to increase its parallel processing capacity, this method can＇t raise the number of the registers on M1PS. And the pipeline processing of the critical byte substitution phase and mix column phase of the AES algorithms could use the idle cycle of the MIPS＇s pipeline cycle, it decrease the critical path of the extension module. It compares the performance of different implementation and the results show that this method reduces the critical path to let the processor run at a high frequency, but it decreases a large area of the chip, also it has the advantage of the flexible programming.

关 键 词：MIPS 高等加密标准(AES) 流水线 指令集扩展 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]