通用数字电路板测试系统硬件设计  

Hardware Design of a General Digital Circuit Board Testing System

作　　者：周博[1] 刘文波[1] 

机构地区：[1]南京航空航天大学自动化学院,江苏南京210016

出　　处：《电子科技》2012年第6期110-114,共5页Electronic Science and Technology

摘　　要：针对传统依靠人工使用示波器、万用表、逻辑分析仪等设备对数字电路板进行测试具有过程复杂、工作量大、可靠性低等缺点,介绍一套通用数字电路板测试系统的硬件设计方案。跟传统数字电路板测试系统相比,文中的设计性能参数更优,主要包括:测试频率最高50 MHz并可调为100 MHz的整数分频;测试电平兼容-6～+9 V且可编程步长为100 mV;测试通道32路,每通道可设为输入输出三态可选且同步工作,存储深度1 Mbit,电流驱动能力达50 mA并有过载保护。The conventional method of using an oscilloscope, muhimeter, logic analyzer or other equipment for digital circuit board testing is complex, time consuming and not reliable. In this paper, the hardware design of a general digital circuit board testing system is introduced. Unlike traditional digital circuit board testing systems, this design has better performance and parameters： the testing frequency can reach 50 MHz and can be set as integer di- vision of 100 MHz; the testing level is compatible to -6 V - ＋ 9 V and can be programmed by 100 mV ; there are up to 32 channels, each channel having 1 Mbit memory depth and 50 mA current drive capability with overload pro- tection, and can work either as input or output for three-state synchronously.

关 键 词：数字电路板测试 嵌入式硬件设计 FPGA 

分 类 号：TN79[电子电信—电路与系统]