基于FPGA的嵌入式数字Q表设计  

Embedded digital Q meter design based on the FPGA

作　　者：王云鹏[1] 续博雄[1] 殷卫真[1] 

机构地区：[1]北京工业大学实验学院,北京101100

出　　处：《电子测量技术》2012年第5期83-86,共4页Electronic Measurement Technology

摘　　要：与传统数字Q表相比,采用FPGA设计的Q表减少了电路复杂程度,体形小,功耗低;电感、电容测量可自动切换量程,测量范围和测量精度具有明显优势。硬件采用FPGA内嵌的32位NiosII处理器作为控制器,能有效地减少分立元件,提高设计效率;电感和Q值测量采用串联谐振法,电容测量采用RC充电法;信源为数字DDS;显示采用LCD模块。软件部分应用嵌入式μC/OS-II多任务实时操作系统。Q表通信采用RS484接口,测量数据可以实时显示。Compared with the traditional digital Q meter,the meter based on the FPGA reduces the circuit complexity, smaller size and lower power consumption,automatic switch the range of inductance and capacitance measurement; the measuring range and precision has obvious advantages. In the hardware, using the 32 bit NiosII processor embedded in FPGA as the controller, it effectively reduce the divided components; and improve the efficiency of design, the parametors of inductors and Q is measured by series resonance method,the signal source is DDS; capacitor part adopts RC charging method;software uses the embedded btC/OS-II real-time multitask operating system, a display module is LCD,the RS484 interface is used for communicate,the measurement data display in the real-time.

关 键 词：嵌入式 DDS 谐振 FPGA 

分 类 号：TH89[机械工程—仪器科学与技术]