一种采用电阻串复用结构的12位SAR ADC  

A 12-Bit SAR A/D Converter with Resistor String Sharing Structure

作　　者：关允超[1] 宁宁[1] 张军[1] 杜翎[1] 吴克军[1] 范洋[1] 冯纯益[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2012年第3期311-314,共4页Microelectronics

基　　金：国家教育部博士点基金(200806141100)

摘　　要：针对带数字校准功能的逐次逼近模/数转换器(SAR ADC),提出将主DAC、校准DAC和基准电压产生电路的电阻串进行复用,从而显著减少了芯片面积,降低了功耗。相比6+6两段电容结构DAC,采用电阻电容混合结构的主DAC和校准DAC节约了37%的版图面积。在0.18μm CMOS工艺下,通过Hspice仿真,SAR ADC的DNL和INL均小于0.4LSB,SNR为75dB。系统正常工作时,总功耗为3.1mW,比不采用电阻串复用的结构减少0.9mW。A new structure was proposed for successive approximation register A/D converter （SAR AIN2） with digital calibration function, in which the main DAC, calibration DAC and reference voltage generator shared the same resistor string. With this technique, chip area and power dissipation could be remarkably reduced. Compared to DAC with 6＋6 two-segment capacitor structure, main DAC and calibration DAC with resistor-capacitor hybrid structure could save about 37% of layout area. Hspice simulation based on 0. 18 gm CMOS process showed that the proposed SAR ADC had a DNL and INL less than 0. 4 LSB and a SNR of 75 dB. For normal operation, the system dissipated a total power of 3.1 mW, which was 0. 9 mW less than the structure with separate resistor strings.

关 键 词：模/数转换器 电阻串复用 逐次逼近寄存器 数字校准 

分 类 号：TN432[电子电信—微电子学与固体电子学]