基于三维Mesh片上网络的双链路互连架构  

Dual-link interconnect architecture for 3-D Mesh-based network on chip

作　　者：孙光[1] 林世俊[1] 张媛媛[1] 苏厉[1] 金德鹏[1] 曾烈光[1] 

机构地区：[1]清华大学电子工程系,微波与数字通信技术国家重点实验室,北京100084

出　　处：《清华大学学报（自然科学版）》2012年第5期632-635,641,共5页Journal of Tsinghua University(Science and Technology)

基　　金：国家自然科学基金资助项目(90607009);国家"八六三"探索类项目(2008AA01Z107)

摘　　要：片上网络(network on chip,NoC)作为一种全新的片上互连通信架构,面积受限,却具有丰富的线资源。而且,三维片上网络的层间互连线很短,同时提供了在第三维度上的互连扩展性。根据这些特性,该文提出了一种基于三维Mesh片上网络的双链路互连架构。在垂直方向上,该架构采用双链路互连,使其通信带宽加倍;而且,跨层连接的垂直链路降低了消息传输的路由跳数。这些都带来网络平均延时的降低和最大吞吐量的提高,却仅仅增加一些控制逻辑电路。仿真结果验证了理论分析。与传统的单链路架构相比,该架构以较小的面积开销换取了较大的性能提高。Network on chip（NoC）,which is a new on chip communication infrastructure,is very sensitive to its area overhead,but has abundant wire resources.Furthermore,three dimensional（3-D） NoC designs provide short interconnection lengths between layers with interconnect scalability in the third dimension.This paper describes a dual-link interconnect architecture for 3-D mesh-based NoC designs.The design has dual links in the vertical direction to improve the communication bandwidth.Some of the vertical links cross through the intermediate layers to reduce the number of hops of messages in the third dimension.These both reduce the average latency and increase the maximal throughput with just a few additional control logic circuits.Simulations verify the theoretical analysis and show the performance advantages of this architecture with a relatively small increment of area overhead compared with the traditional one-link architecture.

关 键 词：片上网络 双链路 延时 吞吐量 面积开销 

分 类 号：TN43[电子电信—微电子学与固体电子学]